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general description the MAX11043 features 4 single-ended or differential channels of simultaneous-sampling adcs with 16-bit resolution. the MAX11043 contains a versatile filter block and programmable-gain amplifier (pga) per channel. the filter consists of seven cascaded 2nd- order filter sections for each channel, allowing the con- struction of a 14th-order filter. the filter coefficients are user-programmable. configure each 2nd-order filter as lowpass (lp), highpass (hp), or bandpass (bp) with optional rectification. gain and phase mismatch of the analog signal path is better than -50db. the adc can sample up to 800ksps per channel. a 40mhz serial interface provides communication to and from the device. the spi interface provides through- put of 1600ksps; 4 channels at 400ksps per channel or 2 channels at 800ksps per channel. a software-selec- table scan mode allows reading the adc results while simultaneously updating the dac. other features of the MAX11043 include an internal (+2.5v) or external (+2.0v to +2.8v) reference, power-saving modes, and a pga with gains of 1 to 64. the pga includes an equalizer (eq) function that automatically boosts low- amplitude, high-frequency signals for applications such as cw-chirp radar. the MAX11043 includes two 8-bit coarse dacs that set the high and low references for a second-stage 12-bit fine dac, typically used for vco control. use software controls to write to the dac or step the dac up and down under hardware control in programmable steps. the device operates from a +3.0v to +3.6v supply. the MAX11043 is available in a 40-pin, 6mm x 6mm tqfn package and operates over the extended -40? to +125? temperature range. applications automotive radar systems data acquisition systems industrial controls power-grid monitoring features ? 4 single-ended or differential channels of simultaneous-sampling, 16-bit adcs ? ?0 lsb inl, ? lsb dnl, no missing codes ? 90db sfdr, -86db thd, 76db sinad, 77db snr at 100khz input ? pga with gain of 1, 2, 4, 8, 16, 32, or 64 for each channel ? eq function automatically boosts high-frequency, low-amplitude signals ? seven-stage internal programmable biquad filters per channel ? high throughput, 400ksps per channel for 4 channels or 800ksps per channel for 2 channels ? dual-stage dac two 8-bit coarse reference dacs 12-bit fine dac ? +2.5v internal reference or +2.0v to +2.8v external reference ? single +3.3v operation ? shutdown and power-saving modes ? 40-pin, 6mm x 6mm tqfn package ? -40? to +125? operating temperature MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ________________________________________________________________ maxim integrated products 1 MAX11043 tqfn + top view 35 36 34 33 12 11 13 refa ainap avdd agnd dgnd 14 ainbn refdacl aout agnd refdach refdac refd dgnd dvdd 12 refbp 4567 27 28 29 30 26 24 23 22 i.c. aincn eoc i.c. sclk din ainan avdd 3 25 37 aincp dout 38 39 40 refc refb ainbp cs convrun dacstep *connect ep to agnd. *ep agnd 32 15 oscin aindp 31 16 17 18 19 20 oscout dvdd dvreg up/dwn shdn 8910 21 aindn pin configuration ordering information 19-4250; rev 0; 8/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX11043atl+ -40? to +125? 40 tqfn-ep* + denotes a lead-free/rohs-compliant package. * ep = exposed pad. spi is a trademark of motorola, inc.
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v avdd = +3.0v to +3.6v, v dvdd = +3.0v, c dvreg = 10?, v agnd = v dgnd = 0, common-mode input voltage = avdd/2, v refbp = v refa = v refb = v refc = v refd = +2.5v (external reference), v refdac = v refdach = +1.25v (external reference), v refdacl = 0, c refbp = c refa = c refb = c refc = c refd = c refdac = 1?, f sclk = 38.4mhz, f exclk = 38.4mhz (external clock applied to oscin), clock divider set to 4, shdn = dacstep = up/ dwn = dgnd, convrun = dvdd, all analog inputs driven directly through a series 150 /330pf anti-alias filter, pga gain = 1. default filters and gain settings. t a = t min to t max , unless otherwise noted (note 1). typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avdd to agnd ....................................................-0.3v to +4.0v dvdd to dgnd .....................................................-0.3v to +4.0v dvreg to dgnd...................................................-0.3v to +3.0v agnd to dgnd.....................................................-0.3v to +0.3v analog i/o, refdach, refdacl, refa, refb, refc, refd, aout, refdac, refbp to agnd......-0.3v to (avdd + 0.3v) up/ dwn , convrun, shdn, dacstep, eoc , digital i/o, oscin, oscout to dgnd ....................-0.3v to (dvdd + 0.3v) maximum current into any pin except avdd, dvdd, dvreg, agnd, dgnd...............................................................?0ma continuous power dissipation (t a = +70?) tqfn multilayer board (derate 37mw/? above +70?) ................................2963mw tqfn single-layer board (derate 26.3mw/? above +70?) ..........................2105.3mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range ............................-65? to +150? lead temperature (soldering, 10s) ................................+300? parameter symbol conditions min typ max units sigma-delta adc resolution n 16 bits integral nonlinearity inl -16 ? lsb differential nonlinearity dnl guaranteed monotonic -1 +1 lsb offset error oe -35 +35 mv offset-error drift ?0 ?/? gain error ge trimmed with 150 /330pf anti-alias filter -1 +1 % gain temperature coefficient ?0 ppm/? channel gain-error matching complete analog signal path -0.25 +0.25 % channel offset matching complete analog signal path -60 +60 mv dynamic performance (pga disabled, pga gain = 1 x (25khz -1db full-scale signal)) maximum full-scale input adc modulator gain = 1 1.2 v p-p input-referred noise spectral density 100khz 85 nv/ hz second harmonic to fundamental -80 -93 db third harmonic to fundamental -80 -110 db spurious-free dynamic range sfdr 77 102 db channel-to-channel isolation unused channels are shorted and unconnected 85 108 db channel phase matching between all channels, including complete analog signal path -0.05 +0.05 degrees
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units dynamic performance (pga enabled, pga gain = 8 x (25khz -1db full-scale signal)) maximum full-scale input adc modulator gain = 1 150 mv p-p input-referred noise spectral density 100khz 20 nv/ hz second harmonic to fundamental -92 db third harmonic to fundamental -94 db spurious-free dynamic range sfdr 100 db channel-to-channel isolation unused channels are shorted and unconnected 110 db channel phase matching between all channels, including complete analog signal path -0.05 +0.05 degrees dynamic performance (pga enabled, pga gain = 16 x (25khz -1db full-scale signal)) maximum full-scale input adc modulator gain = 1 75 mv p-p input-referred noise spectral density 100khz 15 nv/ hz second harmonic to fundamental -99 db third harmonic to fundamental -93 db spurious-free dynamic range sfdr 97 db channel-to-channel isolation unused channels are shorted and unconnected 106 db channel phase matching between all channels, including complete analog signal path -0.075 +0.075 degrees dynamic performance (eq mode (5khz -1db full-scale signal, config_ register bit 3 = 1)) maximum full-scale input adc modulator gain = 1 (note 2) 800 mv p-p input-referred noise spectral density 100khz 6 nv/ hz second harmonic to fundamental -80 -90 db third harmonic to fundamental -77 -98 db spurious-free dynamic range sfdr input referred (note 3) 80 89 db electrical characteristics (continued) ((v avdd = +3.0v to +3.6v, v dvdd = +3.0v, c dvreg = 10?, v agnd = v dgnd = 0, common-mode input voltage = avdd/2, v refbp = v refa = v refb = v refc = v refd = +2.5v (external reference), v refdac = v refdach = +1.25v (external reference), v refdacl = 0, c refbp = c refa = c refb = c refc = c refd = c refdac = 1?, f sclk = 38.4mhz, f exclk = 38.4mhz (external clock applied to oscin), clock divider set to 4, shdn = dacstep = up/ dwn = dgnd, convrun = dvdd, all analog inputs driven directly through a series 150 /330pf anti-alias filter, pga gain = 1. default filters and gain settings. t a = t min to t max , unless otherwise noted (note 1). typical values are at t a = +25?.)
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 4 _______________________________________________________________________________________ electrical characteristics (continued) ((v avdd = +3.0v to +3.6v, v dvdd = +3.0v, c dvreg = 10?, v agnd = v dgnd = 0, common-mode input voltage = avdd/2, v refbp = v refa = v refb = v refc = v refd = +2.5v (external reference), v refdac = v refdach = +1.25v (external reference), v refdacl = 0, c refbp = c refa = c refb = c refc = c refd = c refdac = 1?, f sclk = 38.4mhz, f exclk = 38.4mhz (external clock applied to oscin), clock divider set to 4, shdn = dacstep = up/ dwn = dgnd, convrun = dvdd, all analog inputs driven directly through a series 150 /330pf anti-alias filter, pga gain = 1. default filters and gain settings. t a = t min to t max , unless otherwise noted (note 1). typical values are at t a = +25?.) parameter symbol conditions min typ max units channel-to-channel isolation unused channels are shorted and unconnected 80 104 db channel phase matching between all channels, including complete analog signal path -0.12 +0.12 degrees dynamic performance (all modes) all 4 channels 400 conversion rate 2 channels only 800 ksps minimum throughput 5 ksps power-supply rejection ratio dcpsrr 50 db analog inputs (ainap/ainan, ainbp/ainbn, aincp/aincn, aindp/aindn) absolute voltage any input (note 4) 0 avdd v diff = 1 25 direct input to adc, gain = 1 diff = 0 100 direct input to adc, gain = 2 7 direct input to adc, gain = 4 or 8 7 input impedance (note 5) pga gain = 16 5.5 k input capacitance eq mode only 50 pf eq filter (analog and digital) unity-gain frequency default 5 khz lower transition frequency default, from 40db/decade to 0db/decade 190 khz upper transition frequency default, from 0db/decade to -80db/decade 205 khz lp filter -3db corner frequency default 205 khz reference input ref_ input voltage range v ref_ 2 2.5 2.8 v input current 150 ? refbp input voltage range v refbp 2 2.5 2.8 v input current 700 ? refdac input voltage range v refdac 1 1.25 1.4 v input resistance 17 k
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac _______________________________________________________________________________________ 5 electrical characteristics (continued) ((v avdd = +3.0v to +3.6v, v dvdd = +3.0v, c dvreg = 10?, v agnd = v dgnd = 0, common-mode input voltage = avdd/2, v refbp = v refa = v refb = v refc = v refd = +2.5v (external reference), v refdac = v refdach = +1.25v (external reference), v refdacl = 0, c refbp = c refa = c refb = c refc = c refd = c refdac = 1?, f sclk = 38.4mhz, f exclk = 38.4mhz (external clock applied to oscin), clock divider set to 4, shdn = dacstep = up/ dwn = dgnd, convrun = dvdd, all analog inputs driven directly through a series 150 /330pf anti-alias filter, pga gain = 1. default filters and gain settings. t a = t min to t max , unless otherwise noted (note 1). typical values are at t a = +25?.) parameter symbol conditions min typ max units refdac_ input voltage range v refdac_ 0 1.4 v input resistance 150 k internal reference reference voltage v refbp 2.45 2.5 2.55 v reference temperature coefficient 100 ppm/ c crystal oscillator (max esr 100 , 22pf load capacitors to dgnd) maximum crystal operating frequency epson electronics ma-505 (16mhz) 16 mhz external clock input frequency range external clock applied to oscin 4 40 mhz stability excluding crystal 25 ppm startup time epson electronics ma-505 (16mhz) 10 ms oscin input low voltage when driven with external clock source 0.3 x dvdd v oscin input high voltage when driven with external clock source 0.7 x dvdd v oscin leakage current -5 +5 ? digital inputs input high voltage v ih 0.7 x dvdd v input low voltage v il 0.3 x dvdd v input hysterisis 15 mv input leakage current i in v in = 0 or dvdd -1 +1 ? input capacitance c in 15 pf digital outputs output-voltage high v oh i source = 0.8ma dvdd - 0.6 v output-voltage low v ol i sink = 1.6ma 0.4 v three-state leakage current dout only -1 +1 ? three-state output capacitance dout only 15 pf voltage regulator regulated digital supply voltage dv reg internal use only 2.5 v power requirements analog supply voltage 3.0 3.6 v digital supply voltage 3.0 3.6 v
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 6 _______________________________________________________________________________________ electrical characteristics (continued) ((v avdd = +3.0v to +3.6v, v dvdd = +3.0v, c dvreg = 10?, v agnd = v dgnd = 0, common-mode input voltage = avdd/2, v refbp = v refa = v refb = v refc = v refd = +2.5v (external reference), v refdac = v refdach = +1.25v (external reference), v refdacl = 0, c refbp = c refa = c refb = c refc = c refd = c refdac = 1?, f sclk = 38.4mhz, f exclk = 38.4mhz (external clock applied to oscin), clock divider set to 4, shdn = dacstep = up/ dwn = dgnd, convrun = dvdd, all analog inputs driven directly through a series 150 /330pf anti-alias filter, pga gain = 1. default filters and gain settings. t a = t min to t max , unless otherwise noted (note 1). typical values are at t a = +25?.) parameter symbol conditions min typ max units pga disabled 60 80 analog supply current i avdd all channels selected pga enabled 120 140 ma digital supply current i dvdd 26 40 ma i avdd 5 shutdown current i dvdd 5 ma static accuracy?ine dac (c l = 200pf, r l = 10k ) resolution 12 bits integral nonlinearity inl -5 +5 lsb differential nonlinearity dnl guaranteed monotonic -1 +1 lsb offset error -70 +70 mv offset-error temperature coefficient ?0 ?/? gain error -2 0 % gain-error temperature coefficient ?0 ppm of fs/? dynamic performance?ine dac (c l = 200pf, r l = 10k ) output noise f = 0.1hz to 1mhz 200 ? rms dac glitch impulse major carry transition 12 nv ? s 25% to 75% fs 3 voltage-output settling time 1% fs 1.5 ? voltage-output slew rate 0.6 v/? static accuracy?efdach and refdacl resolution 8 bits integral nonlinearity inl -0.5 +0.5 lsb differential nonlinearity dnl -0.2 +0.2 lsb offset error -30 +30 mv offset-error temperature coefficient ?0 ?/? gain error -5 +5 lsb gain-error temperature coefficient ?0 ppm of fs/? flash memory programming endurance 10,000 cycles data retention t a = +85? 15 years
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac _______________________________________________________________________________________ 7 note 1: devices 100% production tested at t a = +125?. guaranteed by design and characterization to t a = -40?. note 2: full scale in analog eq mode decreases with increasing frequency at a rate of 20db/decade from 5khz. if digital eq is also used, full scale decreases with increasing frequency at 40db/decade from 5khz. note 3: sfdr in the eq mode is normalized to the input by subtracting the analog eq gain at each frequency (20db/decade) from the fft results. note 4: the absolute input voltage range is 0 to avdd. for optimal performance, use a common-mode voltage of avdd/2. note 5: switched capacitor input impedance is proportional to 1/fc. where f is the sampling frequency and c is the input capacitance. electrical characteristics (continued) ((v avdd = +3.0v to +3.6v, v dvdd = +3.0v, c dvreg = 10?, v agnd = v dgnd = 0, common-mode input voltage = avdd/2, v refbp = v refa = v refb = v refc = v refd = +2.5v (external reference), v refdac = v refdach = +1.25v (external reference), v refdacl = 0, c refbp = c refa = c refb = c refc = c refd = c refdac = 1?, f sclk = 38.4mhz, f exclk = 38.4mhz (external clock applied to oscin), clock divider set to 4, shdn = dacstep = up/ dwn = dgnd, convrun = dvdd, all analog inputs driven directly through a series 150 /330pf anti-alias filter, pga gain = 1. default filters and gain settings. t a = t min to t max , unless otherwise noted (note 1). typical values are at t a = +25?.) parameter symbol conditions min typ max units spi interface sclk clock period t cp 25 ns sclk pulse-width high t ch 10 ns sclk pulse-width low t cl 10 ns sclk rise to dout transition t dot c load = 20pf 1 15 ns cs fall to sclk rise setup time t css 10 ns sclk rise to cs rise setup time t csh 5ns din to sclk rise setup time t ds 10 ns din to sclk rise hold time t dh 0ns cs pulse-width high t cspwh 10 ns cs rise to dout disable t dod c load = 20pf 20 ns cs fall to dout enable t doe c load = 20pf 1 ns eoc fall to cs fall t rds 10 ns typical operating characteristics (v avdd = +3.3v, v dvdd = +3.0v, f sclk = f exclk = 19.2mhz, v refbp , v ref_ = +2.5v, common-mode input voltage = avdd/2, t a = +25?, unless otherwise noted.) inl vs. code MAX11043 toc01 code (lsb) inl (lsb) 49152 32768 16384 -4 -3 -2 -1 0 1 2 3 4 5 -5 0 65536 lp mode gain = 1 400ksps fft lp mode MAX11043 toc02 frequency (khz) amplitude (dbfs) 180 160 140 120 100 80 60 40 20 -100 -80 -60 -40 -20 0 -120 0 200 f in = 50khz gain = 1 800ksps fft lp mode MAX11043 toc03 frequency (khz) amplitude (dbfs) 350 300 250 200 150 100 50 -120 -100 -80 -60 -40 -20 0 -140 0400 f in = 50khz gain = 1
fine dac settling 75% to 25% fs step MAX11043 toc10 500mv/div 0v fine dac settling 1% step-up MAX11043 toc11 1 s/div 20mv/div 1200mv MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 8 _______________________________________________________________________________________ 400ksps fft eq mode MAX11043 toc04 frequency (khz) amplitude (dbfs) 180 160 140 120 100 80 60 40 20 -100 -80 -60 -40 -20 0 -120 0200 f in = 5khz v inp-p = 560mv 800ksps fft eq mode MAX11043 toc05 frequency (khz) amplitude (dbfs) -120 -100 -80 -60 -40 -20 0 -140 0 400 200 f in = 100khz v inp-p = 1.4mv sinad vs. input amplitude MAX11043 toc06 input amplitude (dbfs) sinad (db) -10 -30 -70 -50 -20 -40 -80 -60 -10 0 10 20 30 40 50 60 70 80 -20 -90 0 1khz 10khz 50khz fine dac dnl vs. code MAX11043 toc07 code (lsb) dnl (lsb) 3072 2048 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 fine dac inl vs. code MAX11043 toc08 code (lsb) inl (lsb) 3072 2048 1024 -4 -3 -2 -1 0 1 2 3 4 5 -5 0 4096 fine dac settling 25% to 75% fs step MAX11043 toc09 500mv/div 0v typical operating characteristics (continued) (v avdd = +3.3v, v dvdd = +3.0v, f sclk = f exclk = 19.2mhz, v refbp , v ref_ = +2.5v, common-mode input voltage = avdd/2, t a = +25?, unless otherwise noted.)
MAX11043 fine dac settling 1% step-down MAX11043 toc12 1 s/div 20mv/div 1200mv 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac _______________________________________________________________________________________ 9 fine dac noise floor frequency (khz) 140 120 100 40 20 180 160 80 60 200 MAX11043 toc13 0 20dbm/div 0dbm coarse dac dnl vs. code MAX11043 toc14 code (lsb) dnl (lsb) 192 128 64 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0256 codes 3 to 255 dach dacl co ar s e da c inl vs. code MAX11043 toc15 code (lsb) inl (lsb) 192 128 64 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 256 codes 3 to 255 dach dacl coarse dac settling time, positive step MAX11043 toc16 2ms/div 200mv/div coarse dac settling time, negative step MAX11043 toc17 2ms/div 200mv/div dvreg voltage vs. temperature MAX11043 toc18 temperature ( c) dvreg voltage (v) 120 100 80 60 40 20 0 -20 2.363 2.364 2.365 2.366 2.367 2.368 2.369 2.362 -40 typical operating characteristics (continued) (v avdd = +3.3v, v dvdd = +3.0v, f sclk = f exclk = 19.2mhz, v refbp , v ref_ = +2.5v, common-mode input voltage = avdd/2, t a = +25?, unless otherwise noted.) power-on reset vs. temperature MAX11043 toc19 temperature ( c) supply voltage (v) 120 100 60 80 02040 -20 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 -40 analog supply digital supply
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 10 ______________________________________________________________________________________ pin description pin name function 1 ainbn channel b analog negative input 2 refa channel a reference bypass. bypass refa with a nominal 1? capacitor to agnd. 3 ainan channel a analog negative input 4 ainap channel a analog positive input 5, 26 avdd analog supply. bypass each avdd with a nominal 1? capacitor to agnd. 6, 24, 33 agnd analog ground. connect agnd inputs together. 7, 23 dgnd digital ground. connect dgnd inputs together. 8, 22 dvdd digital supply. bypass each dvdd with a nominal 1? capacitor to dgnd. 9 dvreg regulated digital core supply. bypass dvreg to dgnd with a 10? capacitor. 10 up/ dwn dac step direction select. drive high to step up, drive low to step down when dacstep is toggled. 11 dacstep dac step input. drive high to move the dac output in the direction of up/ dwn on the next rising edge of the system clock. 12 convrun convert run. drive high to start continuous conversions on all 4 channels. the device is idle when convrun is low. 13 cs active-low serial-interface chip select 14 dout serial-interface data out. data transitions on the rising edge of sclk. 15 din serial-interface data in. data is sampled on the rising edge of sclk. 16 sclk serial-interface clock 17, 35 i.c. internally connected. connect to either agnd or dgnd. 18 eoc active-low end-of-conversion indicator. eoc asserts low to indicate that new data is ready. 19 oscin crystal oscillator/external clock input 20 oscout crystal-oscillator output. leave unconnected when using external clock. 21 shdn active-high shutdown input. drive high to shut down the MAX11043. 25 aout buffered 12-bit fine dac output 27 refdacl fine dac low reference bypass. bypass refdacl with a nominal 1? capacitor to agnd. 28 refdach fine dac high reference bypass. bypass refdach with a nominal 1? capacitor to agnd. 29 refdac coarse dac reference bypass. bypass refdac with a nominal 1? capacitor to agnd. 30 refd channel d reference bypass. bypass refd with a nominal 1? capacitor to agnd. 31 aindn channel d analog negative input 32 aindp channel d analog positive input 34 refbp main reference bypass. bypass refbp with a nominal 1? capacitor to agnd. 36 aincn channel c analog negative input 37 aincp channel c analog positive input 38 refc channel c reference bypass. bypass refc with a nominal 1? capacitor to agnd. 39 refb channel b reference bypass. bypass refb with a nominal 1? capacitor to agnd. 40 ainbp channel b analog positive input ?p exposed pad. connect ep to a ground plane on the pcb to enhance thermal dissipation. internally connected to agnd. not intended as an electrical connection point.
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ______________________________________________________________________________________ 11 flash por crystal oscillator and clock buffer internal regulator +2.5v +2.5v voltage reference serial interface programmable digital filter sigma-delta adc digital supply clock 12-bit dac 8-bit dac r r dacstep up/dwn dout sclk shdn eoc convrun din dvreg oscout oscin aout refdach refdacl refdac refbp refd aindn aindp refc aincn aincp refb ainbn ainbp refa ainap ainan avdd dvdd agnd dgnd MAX11043 programmable digital filter sigma-delta adc programmable digital filter sigma-delta adc programmable digital filter sigma-delta adc pga eq pga eq pga eq pga eq 2x functional diagram
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 12 ______________________________________________________________________________________ detailed description the MAX11043 features 4 single-ended or differential channels of simultaneous-sampling adcs with 16-bit resolution. the MAX11043 contains a versatile filter block and pga per channel. the filter consists of seven cascaded 2nd-order filter sections for each channel allowing the construction of a 14th-order filter. the filter coefficients are user-programmable. configure each 2nd-order filter as a lp filter, hp filter, or bp filter with optional rectification. gain and phase mismatch of the analog signal path is better than -50db. the adcs can sample up to 800ksps per channel. a 40mhz serial interface provides communication to and from the device. the spi interface provides throughput of 1600ksps; 4 channels at 400ksps per channel or 2 channels at 800ksps per channel. a software-selec- table scan mode allows reading the adc results while simultaneously updating the dac. other features of the MAX11043 include an internal (+2.5v) or external (+2.0v to +2.8v) reference, power-saving modes, and a pga with gains of 1 to 64. the pga includes an eq function that automatically boosts low-amplitude, high- frequency signals for applications such as cw-chirp radar. the MAX11043 includes two 8-bit coarse dacs that set the high and low references for a second-stage 12-bit fine dac, typically used for vco control. use software controls to set the dac, or step the dac up and down using hardware control in programmable steps. MAX11043 signal path each of the 4 adc channels features a pga and filter block that feeds the signal to the sigma-delta modula- tor. the pga can either be bypassed, which provides a gain of 1, set to a gain of 8, a gain of 16, or set to ana- log eq mode. for more amplification, set the adc mod- ulator gain to one, two, or four. after the modulator, the result passes through the sinc 5 filter and decimator. seven biquad programmable digital filters isolate the band of interest. read the result using the 40mhz spi interface. see figure 1. analog-to-digital converter the MAX11043 features a quad sigma-delta adc archi- tecture with 4 differential input channels. for single- ended operation, connect the n input to the common-mode voltage or bypass to agnd with a 10? capacitor. all inputs feature a programmable bias gen- erator; see the config_ register (0ch?fh) section. all four adcs convert simultaneously with a maximum modulator sampling rate of 9.6msps; decimated by 12 or 24 for output rates of 800ksps and 400ksps, respec- tively. the spi bus limits the maximum output data rate to 40mbps. sinc 5 filter the sinc 5 filter removes high-frequency noise from the output of the sigma-delta modulator. it also decimates the modulator data by a factor of 12, providing a maxi- mum of 800ksps to the programmable filters when the modulator is operating at 9.6msps. figure 2 shows the frequency characteristics of the sinc 5 filter with the modulator running at 9.6msps. operating the modulator pga and filter modulator with gains of 1, 2, or 4 sinc 5 filter and decimate by 12 spi biquad filter 1 biquad filter 7 in 7 biquad filters in series modg1 modg0 0 0 0 1 1 0 1 1 gain 1 2 4 4 equalizer lp filter and gain 16x lp filter and gain 8x bypass pga and filter modes pdpga pgag eq 1 x x 0 0 0 0 1 0 0 x 1 fine gain adjust chan x fine gain resolution = 16 bits ram por values por values user values user defined equalizer lp filter biquad modes filt 1 0 x range: -4 to +4 decimate by 1 or 2 decimate total decimation 2 24 1 12 decsel 0 1 figure 1. signal path
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ______________________________________________________________________________________ 13 at a lower sample rate causes a proportional reduction in the frequency response of the sinc 5 filter. the total attenuation of the MAX11043 is the sum of the analog filtering, the sinc 5 filter, and the seven stages of pro- grammable filters. equalizer (eq) the eq matches the frequency/gain characteristics of cw-chirp radar systems where the distance to the tar- get is proportional to the measured frequency. distant targets not only have a higher frequency, they have a weaker signal. hence, higher frequencies need more amplification than lower frequencies. the eq provides gain proportional to frequencies up to 190khz, at which point the gain rolls off at 80db/decade. the eq consists of an analog section in the pga and a digital eq created from the biquad filters. the analog eq (pga) provides 20db/decade of gain and the default digital eq provides an additional 20db/decade of gain. together they provide 40db/decade of gain up to 190khz with a gain of 0db at 5khz. variations in the manufacturing process affect the gain and phase of the analog filter. compensation for these variations include adjustments to the digital filter during the manufacture of the MAX11043. use the analog and digital eqs together for optimal performance. for a detailed description of digital-filter customization, refer to the MAX11043 user? guide . conversion and adc reading drive convrun high to initiate a continuous conver- sion on all 4 channels. keep convrun high for the entire conversion process. do not pulse convrun. eoc asserts low when new data is available. initiate a data read prior to the next rising edge of eoc or the result is overwritten. eoc asserts high upon read com- pletion of all active channels. use configa, configb, configc, and configd registers to read single channel data. concatenated data is available in the adcab, adccd, and adcabcd registers. use concatenated registers to ensure simultaneous results are read. see the register functions section for more details. a software-selectable scan mode automatically sends the result from selected channels following the cs falling edge and allows other registers to be simultane- ously updated. to enable scan mode, set schan_ bits high. see the configuration register (08h) section for a detailed description. the adc output is presented in two? complement format (figure 3). digital filter seven cascaded, individually configurable, 2nd-order filter elements make up the digital filter. figure 4 shows the structure of a single filter section. configure these elements as lp, bp, hp, or all pass (ap) filters with optional rectification. filter configuration is transferred from the flash to coefficient ram (c-ram) on power-up. store custom filters permanently in the flash or write directly to c-ram each time on power-up. two sepa- rate sets of programmable coefficients exist for each filter. dual coefficient sets allow rapid filter reconfigura- tion. these filter coefficients are programmed to lp and eq modes at the factory. multiple flash memory pages exist so that custom filters can be created while pre- serving factory-programmed filter coefficients. sinc 5 filter at 9.6msps MAX11043 fig02 frequency (khz) attenuation (db) 1600 1200 800 400 -100 -80 -60 -40 -20 0 -120 0 2000 figure 2. sinc 5 filter frequency response 0 +1 +fs -1 -fs 1000 0000 0000 0000 1000 0000 0000 0001 1000 0000 0000 0010 input voltage (lsb) binary output code 0111 1111 1111 1101 0111 1111 1111 1110 0111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0001 1111 1111 1111 1111 figure 3. two? complement transfer function
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 14 ______________________________________________________________________________________ filter coefficients a1 and b1 are always 1. b3 is limited to -1, 0, and 1. filter coefficients a2, a3, and b2 are stored as 16-bit two? complement values in the range of -4 to +4. gain is limited to the following values 2 4 , 2 2 , 2 0 , 2 -2 , 2 -4 , 2 -6 , 2 -8 , and 2 -10 . for better gain resolution, adjust the fine gain a/b/c/d registers at the input of each filter set. fine gain adjustment has a resolution of 16 bits and a gain range of -4 to +4. set the rect bit to rectify the filter output. figures 5? show the response to a step input of the default filters used for adc trimming. 1/a1 -a2 z -1 -a3 b1 b2 b3 + + + + out in x y rect g abs z -1 figure 4. single programmable 2nd-order filter section sinc 5 filter output MAX11043 fig05 sample output (lsb) 8 6 4 2 500 1000 1500 2000 2500 0 010 figure 5. sinc 5 filter response to a step input
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ______________________________________________________________________________________ 15 programmable gain amplifier each adc channel features an input buffer with input impedance of at least 5k and programmable gain of eight or 16. when set to a gain of one, the signal bypasses the pga to reduce noise. the pga features an optional 20db/decade analog eq mode, with a gain of 0db at 5khz and attenuation above 190khz to reduce out-of-band noise. using the digital eq filter adds another 20db/decade gain. control the eq and pga gain from their respective config_ registers. for additional filtering and equal- ization, use the integrated digital filters. refer to the MAX11043 user? guide for more information. digital-to-analog converter the MAX11043 features a 12-bit fine dac with high and low reference inputs set by the 8-bit, dual tap coarse dac or driven externally. the output buffer of the fine dac has a gain of two and can drive 10k and 200pf in parallel. bypass the refdach and refdacl with a 1? capaci- tor when using the coarse dac to set the reference values, or power down the buffers and drive refdach and refdacl with external references. alternatively drive one of the fine dac references using the coarse dac and the other using an external reference. the fine dac register contains the current value of the output. the output value changes by writing to this reg- ister or by the rising edge of the dacstep input. the dac register updates on the next rising edge of the system clock following the rising edge of the dacstep input. the programmable dacstep register contains the step size. the up/ dwn input sets the direction of the step. drive up/ dwn high to step up, drive low to step down. the coarse 8-bit, dual tap dac generates the high and low reference values for the fine dac. obtain the coarse dac reference from the main reference or by driving the refdac input externally. the main refer- ence, refbp, is divided by two before the coarse dac. when driving refdac, refdach, or refdacl direct- ly, ensure the voltage to the fine dac does not exceed avdd/2 to prevent the output amplifier from saturating. eq filter output MAX11043 fig06 sample output (lsb) 80 60 20 40 -15,000 -10,000 -5000 0 5000 10,000 15,000 20,000 25,000 30,000 35,000 -20,000 0100 figure 6. eq filter response to a step input stage 1 filter output MAX11043 fig08 sample output (lsb) 40 10 30 20 0 500 1000 1500 2000 2500 3000 3500 -500 050 figure 8. stage 1 default filter response to a step input lp filter output MAX11043 fig07 sample output (lsb) 80 60 40 20 500 1000 1500 2000 2500 0 0100 figure 7. lp filter response to a step input
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 16 ______________________________________________________________________________________ reference (refbp) the MAX11043 features an internal 2.5v bandgap ref- erence. bypass refbp with a 1? capacitor or power down the buffer amplifier and drive refbp with an external reference. in internal reference mode, refbp provides the main reference voltage for the MAX11043. refer to www.maxim-ic.com/references for a list of available precision references. in addition to the integrated main reference, there are seven separate references derived from refbp, one for each adc channel, one for the coarse dac, and two (one high and one low) for the fine dac. when using the main reference, bypass each of the references with a 1? capacitor or set the appropriate bits (7?), in the reference (10h) register, to power down the references and drive externally. use external references capable of driving a 700? or total load. clock sources the MAX11043 features an internal 16mhz oscillator that supports either an external crystal or ceramic res- onator. for highest performance, set bit 15 in the con- figuration register to 1 and use an external clock (ex clock) source, up to 40mhz, to drive oscin. a pro- grammable clock divider divides the ex clock by 2, 3, 4, or 6 to generate the adc sample clock. the system clock, used for all digital timing, is twice the adc sam- ple clock. ensure that the minimum ex clock high or low time is greater than 25ns when using the divide-by- 2 or divide-by-3 mode. the system clock, used for all internal timing, is derived from the clock divider setting and the input clock. for optimal performance, derive the spi clock and sys- tem clock from the same source. power saving the MAX11043 features an active-high power-down input, as well as an spi-controlled power-down bit that places the MAX11043 in low-power mode. in addition, the MAX11043 features an independent, spi-controlled, power-down for each adc channel, the dac, and the oscillator. see the configuration register (08h) section for more details. serial communication the spi-compatible interface allows synchronous serial data transfers up to 40mbps. the bandwidth is divided between the dacs and the adc. maximum conversion throughput depends on which read commands are used. the highest conversion rates are obtained by using the scan mode. the second highest rate is obtained by reading concatenated registers. the slow- est method is to read the results individually. configure the spi master for sclk to idle low (sclk is low when cs is asserted). the data at din is latched on the rising edge of sclk. data at dout transitions immediately after the rising edge of sclk. all spi transactions start with a command byte. the command byte selects the address of the register and the mode of operation (read/ write ). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start adr4 adr3 adr2 adr1 adr0 r/ w 0 spi command byte start <7>: start bit. this bit must be 0 for normal operation. adr_<6:2>: device register address bits. see the reg- ister map in table 1. r/ w <1>: read/write bit. 1 = read from device. 0 = write to device.
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ______________________________________________________________________________________ 17 x adr 3 adr 2 adr 1 adr 0 r/w = 0 d7 d6 d5 d4 d3 d2 d1 d0 t ds t cp t cl t ch t csh t dh t css high impedance 0 adr 4 start din sclk dout cs high impedance figure 9. spi 8-bit write operation t dod t dot t css t doe t cp t cl t ch t ds t dh x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 high i m pedance x adr 3 adr 2 adr 1 adr 0 r/w = 1 adr 4 start 0 din sclk cs dout high i m pedance figure 10. spi 8-bit read operation
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 18 ______________________________________________________________________________________ address register name function bits 00h adca adc channel a result register 16/24 01h adcb adc channel b result register 16/24 02h adcc adc channel c result register 16/24 03h adcd adc channel d result register 16/24 04h adcab adc channels a and b results register 32/48 05h adccd adc channels c and d results register 32/48 06h adcabcd adc channels a, b, c, and d results register 64/96 07h status status register 8 08h configuration configures the device 16 09h dac fine dac value 16 0ah dacstep step size for dac increment/decrement function 16 0bh dach/dacl high and low coarse dac values 8 + 8 0ch configa adc channel a configuration 16 0dh configb adc channel b configuration 16 0eh configc adc channel c configuration 16 0fh configd adc channel d configuration 16 10h reference/delay sets the operation state of the reference and buffers 16 11h again channel a fine gain 16 12h bgain channel b fine gain 16 13h cgain channel c fine gain 16 14h dgain channel d fine gain 16 15h filter coefficient address selects the filter coefficient to read or write. this autoincrements each time the coefficient data register is accessed. 8 16h filter coefficient data out coefficient rams output data 32 17h filter coefficient data in filter coefficient data 32 18h flash mode flash mode selection register 8 19h flash addr flash address register 16 1ah flash data in flash data in register 16 1bh flash data out flash data out register 16 1ch reserved 1dh reserved 1eh reserved 1fh reserved register map table 1. spi register map
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ______________________________________________________________________________________ 19 register functions adca, adcb, adcc, and adcd result registers (00h?3h) the adc channel a, b, c, and d result registers pro- vide the result data from the 4 adc channels. eoc asserts low when new data is available. initiate a data read prior to the next rising edge of eoc or the result is overwritten. set bit 5 of the configuration register 08h high to read the data out in 24-bit resolution or set bit 5 low to read the data out in 16-bit resolution. adcab, adccd, and adcabcd result registers (04h?6h) registers adcab, adccd, and adcabcd contain concatenated adc results ensuring simultaneous results are read. this reduces the risk of reading sam- ples delayed by one cycle from channel to channel. set bit 5 of the configuration register 08h high to read the data out in 24-bit resolution or set bit 5 low to read the data out in 16-bit resolution. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x flash busy boot oflga oflgb oflgc oflgd status register (07h) the status register contains the channel overflow flags and por bits. x<7:6>: don?-care bits. flash busy<5>: do not start a new flash operation until this is 0. boot<4>: power-on reset flag. oflg_<3:0>: channel overflow flag, one per channel. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 extclk clkdiv1 clkdiv0 pd pda pdb pdc pdd configuration register (08h) extclk<15>: external clock select. 1 = logic-level clock supplied on oscin. 0 = crystal or resonator connected between oscin and oscout (default). clkdiv1:clkdiv0<14:13>: clock divider ratio (ex clock : adc sample clock). 00 = 1:2 clock divider. 01 = 1:3 clock divider. 10 = 1:4 clock divider. 11 = 1:6 clock divider (default). pd<12>: power-down analog circuitry (reference and spi interface remains active). 1 = low-power mode. 0 = normal operation (default). pd_<11:8>: adc power-down for each channel (a, b, c, and d). 1 = powers down analog signal path. 0 = normal operation (default). pddac< 7>: dac power-down. 1 = fine dac buffer powered down. 0 = normal operation (default). pdosc<6>: oscillator power-down. 1 = oscillator powered down (disconnects ex clock in ex clock mode). 0 = normal operation (default). 24bit<5>: adc output data format. 1 = adc data output as 24 bits. 0 = adc data output as 16 bits (default). use the 24-bit adc output in conjunction with external digital filtering to improve signal-to-noise ratio. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pddac pdosc 24bit schana schanb schanc schand decsel
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 20 ______________________________________________________________________________________ schan_<4:1>: automatic adc result output for each channel (a, b, c, and d). 1 = adc channel data is output on dout each time a new result is valid in the sequence, a, b, c, and d. 0 = adc data is not presented automatically for this channel (default). when schan_ = 1, the selected adc channel data is automatically presented on dout each time eoc asserts low in the sequence a, b, c, and d with the unselected channels omitted. the data transitions on the rising edge of sclk. force cs low to initiate trans- mission. cs can go high between results. the msb of the first selected adc channel outputs immediately after the falling edge of eoc . eoc goes high after the last bit of the selected channels clocks out or one clock cycle before the next result is ready. insufficient sclk pulses result in truncated data. extra clock pulses give an undefined output. in scan mode, keep din high or write data to the MAX11043 as usual. in scan mode, the MAX11043 ignores requests for data reads. decsel<0>: decimate select. 1 = decimate by 12. 0 = decimate by 24 (default). set decsel high to decimate the adc result by 12, doubling the number of samples. the spi interface is limited to 40mbps. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 x x x x dac11 dac10 dac9 dac8 fine dac register (09h) x<15:12>: don?-care bits. dac_<11:0>: contains current fine dac output value. when using the dacstep input to change the dac value, this register updates to the new value on the next rising edge of the system clock following the rising edge of dacstep. the power-on default is 0. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac7 dac6 dac5 dac4 dac3 dac2 dac1 dac0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 x x x x dacstep11 dacstep10 dacstep9 dacstep8 dacstep register (0ah) x<15:12>: don?-care bits. dacstep11:dacstep0<11:0>: provides the size of the dac step. the value is positive only and the up/ dwn input is used to set the direction. the value in the fine dac register updates on the next rising edge of the system clock following the rising edge of the dacstep input. the power-on default is 0. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dacstep7 dacstep6 dacstep5 dacstep4 dacstep3 dacstep2 dacstep1 dacstep0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 dach7 dach6 dach5 dach4 dach3 dach2 dach1 dach0 coarse dach/dacl register (0bh) dach7:dach0<15:8>: high coarse dac value. dacl7:dacl0<7:0>: low coarse dac value. coarse dac sets high and low references for the fine dac. the power-on default is 0. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dacl7 dacl6 dacl5 dacl4 dacl3 dacl2 dacl1 dacl0
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ______________________________________________________________________________________ 21 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 x x x bdac3 bdac2 bdac1 bdac0 diff config_ register (0ch?fh) this register sets the gain of each adc channel and selects one of the default filters or eq function. x<15:13>: don?-care bits. bdac3:bdac0<12:9>: sets the input bias voltage for ac-coupled signals when enbias_ is set to 1. 0000 = 33% of avdd. 0001 = 35% of avdd. 0010 = 38% of avdd. 0011 = 40% of avdd. 0100 = 42% of avdd. 0101 = 44% of avdd. 0110 = 46% of avdd. 0111 = 48% of avdd. 1000 = 50% of avdd. 1001 = 52% of avdd. 1010 = 54% of avdd. 1011 = 56% of avdd. 1100 = 58% of avdd. 1101 = 60% of avdd. 1110 = 62% of avdd. 1111 = 65% of avdd. diff<8>: input mode select bit. 1 = normal operation in all modes. 0 = use for a 2x input signal range in lp, gain = 1 mode. note that thd degrades. eq<7>: eq function. 1 = analog eq enabled. 0 = analog eq disabled (default). modg1:modg0<6:5>: adc modulator gain. 00 = 1 (default). 01 = 2. 10 = 4. 11 = 4. pdpga<4>: pga power-down control. 1 = pga powered down, gain = 1. 0 = pga powered, pga gain set by pgag (default). filt<3>: programmable filter select. 1 = use preprogrammed lp filter. 0 = use preprogrammed eq filter (default). pgag<2>: high pga gain setting. 1 = pga, gain = 16. 0 = pga, gain = 8 (default). enbiasp<1>: positive input bias enable. bias voltage set by bdac3:bdac0. 1 = selfbiasing enabled. 0 = selfbiasing disabled (default). enbiasn<0>: negative input bias enable. bias volt- age set by bdac3:bdac0. 1 = selfbiasing enabled. 0 = selfbiasing disabled (default). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eq modg1 modg0 pdpga filt pgag enbiasp enbiasn
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 22 ______________________________________________________________________________________ bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0 0 0 purge4 purge3 purge2 purge1 purge0 reference register (10h) reserved<15:13>: reserved. set to 0. purge4:purge0<12:8>: filter purge interval. straight binary. 00h = first available sample is presented (default). 1fh = 31 results are discarded. digital filters retain a history of past input data. at power-up and when changing the signal path, old data requires purging before new output data is valid. purge4(msb):purge0 determine the number of sam- ples to discard before a new result is valid. each time convrun is taken high, n results are discarded before eoc asserts low (where n is the decimal equiva- lent of the binary representation of purge4:purge0). results prior to n+1 are overwritten. eoc asserts for results n+1, n+2, n+3, etc., as long as convrun remains high. taking convrun low and then high invokes another purge. purging of the sinc 5 filter requires five readings if decsel (configuration register 08h, bit 0) = 1 and three readings if decsel = 0. the minimum total purge interval of the seven cascaded filters is one reading if not used. if the filters are used, the total latency of the programmable filters is the sum of the latency caused by each stage. set the appropriate delay for filter purg- ing and settling time. extref<7>: main reference selection. 1 = external reference applied to refbp, internal refer- ence buffer powered down. 0 = internal reference, bypass refbp with 1? to agnd (default). exbuf_<6:3>: adc reference selection for each channel. 1 = external reference applied to ref_ input, internal switch open. 0 = using main internal reference, bypass ref_ with 1? to agnd (default). exbufdac<2>: coarse dac reference selection. 1 = external reference applied to refdac, internal ref- erence buffer powered down. 0 = using main internal reference, bypass refdac with 1? to agnd (default). exbufdach<1>: high reference for fine dac. 1 = external reference applied to refdach, internal reference buffer powered down. 0 = using high output from coarse dac as reference, bypass refdach with 1? to agnd (default). exbufdacl<0>: low reference for fine dac. 1 = external reference applied to refdacl, internal reference buffer powered down. 0 = using low output from coarse dac as reference, bypass refdacl with 1? to agnd (default). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 extref exbufa exbufb exbufc exbufd exbufdac exbufdach exbufdacl
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ______________________________________________________________________________________ 23 fine gain register gain 7fffh (4 ?1/8192) 4000h 2 2001h 8193/8192 2000h 1 (default) 1fffh 8191/8192 1000h 0.5 0800h 0.25 fine gain a/b/c/d registers (11h?4h) fine gain for each channel is a two? complement binary value (8192 x desired gain). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chan1 chan0 adr5 adr4 adr3 adr2 adr1 adr0 filter coefficient address register (15h) chan_<7:6>: channel selection. 00 = channel a (default). 01 = channel b. 10 = channel c. 11 = channel d. adr5:adr0<5:0>: address pointer for c-ram con- taining filter coefficients (default = 0). filter coefficient data out register (16h) this is a 32-bit register that contains the data from a c-ram read operation. filter coefficient data in register (17h) this is a 32-bit register that contains the data for a c-ram write operation. default = 0.
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 24 ______________________________________________________________________________________ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fm2 (flashmode2) fm1 (flashmode1) fm0 (flashmode0) 0xxx flash busy (read only) flash mode register (18h) write allowed only if flash busy bit is zero. fm2:fm0<7:5>: flash operation (default 0). 000 = no operation. 001 = write data in flash data in register to flash. 010 = erase data in the selected page. 011 = mass erase the flash. 100 = no operation. 101 = read data from flash into data out register. 110 = transfer data from flash to c-ram. 111 = no operation. reserved<4>: reserved. set to 0. x<3:1>: don?-care bits. flash busy<0>: flash busy flag. 1 = flash busy. 0 = flash ready. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 x x x x x page2 page1 page0 flash address register (19h) write allowed only if flash busy bit is zero (18h bit 0 or status register) (default = 0). x<15:11> : don?-care bits. page2:page0<10:8>: page selection. 000 = page 0 (default). 001 = page 1. 010 = page 2. 011 = page 3. 100 = page 4. 101 = page 5. 110 = page 6. 111 = page 7. adr7:adr0<7:0>: address pointer flash word con- taining filter coefficients (default = 0). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adr7 adr6 adr5 adr5 adr3 adr2 adr1 adr0
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ______________________________________________________________________________________ 25 flash data in register (1ah) write allowed only if flash busy bit is zero. this is a 16-bit register that contains the data for a flash write operation. default = 0. flash data out register (1bh) this is a read-only register. data is valid only if flash busy is zero. this is a 16-bit register that contains the data for a flash read operation. flash and c-ram register map the flash memory consists of 2048 words by 16 bits. the 3 msbs of the flash address select one of eight pages of 256 words each. page zero contains the default filter coefficients for channels a and b. page one contains the default filter coefficients for channels c and d. use pages two and three for the coefficients of custom filters. when the first word on page two con- tains a nonzero value, the MAX11043 loads these pages into c-ram at power-up instead of the default values from pages zero and one. flash pages zero and one include trim data. unique trim data optimizes the performance of each MAX11043. to maintain optimum performance when using custom filters, copy the trim data from flash pages zero and one to the correspond- ing locations in flash pages two and three or to c-ram when writing directly to c-ram. further optimization of the MAX11043 is achieved through stage one filter coefficients for each channel. when using custom filters, copy stage one coefficients from pages zero and one to the corresponding loca- tions in flash pages two and three or to c-ram when writing directly to c-ram. table 2 identifies the default stage one filters (eq and lp) for the MAX11043. for custom filters, use stages two through seven first, and only change the stage one coefficients when all seven stages require customization. the flash addresses below are for channel a; for chan- nel b add 80h, for channel c add 100h, and for channel d add 180h. to write to pages two and three of flash, add 200h to the above values. to load the coefficients directly to c-ram, create a 32- bit data word by concatenating the data in adjacent flash locations as shown in table 3. the c-ram addresses below are for channel a; for channel b add 40h, for channel c add 80h, and for channel d add c0h. multiple addresses exist for some stage 1 filter coeffi- cients as shown in table 3. the address accessed by the filter depends on the configuration bits as shown in table 2. filter first stage eq pgapd modg pgag eq filter stage 1 (c-ram address 03h?5h) 1 0 xx x lp filter for adc gain of 1, 2, and 4; stage 1 (c-ram address 1dh?fh) x 1 xx x lp filter for adc gain of 8; stage 1 (c-ram address 3dh?fh) 0 0 00 0 lp filter for adc gain of 16; stage 1 (c-ram address 23h?5h) 0 0 xx 1 table 2. stage one filter selection c-ram address flash address msb for c-ram lsb for c-ram 00h not used 00h 01h* eq gain trim for gain = 1 02h not used 01h 03h user trim for eq gain, default = 2000h 04h not used 02h 05h not used 06h* eq filter gain for filter stage 1 03h 07h* eq filter coefficient a2 for filter stage 1 table 3. c-ram and flash memory map
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 26 ______________________________________________________________________________________ c-ram address flash address msb for c-ram lsb for c-ram 08h not used 04h 09h* eq filter coefficient a3 for filter stage 1 0ah* eq filter coefficient b3 and rectify bit for filter stage 1 05h 0bh* eq filter coefficient b2 for filter stage 1 0ch eq filter gain for filter stage 2 06h 0dh eq filter coefficient a2 for filter stage 2 0eh not used 07h 0fh eq filter coefficient a3 for filter stage 2 10h eq filter coefficient b3 and rectify bit for filter stage 2 08h 11h eq filter coefficient b2 for filter stage 2 12h eq filter gain for filter stage 3 09h 13h eq filter coefficient a2 for filter stage 3 14h not used 0ah 15h eq filter coefficient a3 for filter stage 3 16h eq filter coefficient b3 and rectify bit for filter stage 3 0bh 17h eq filter coefficient b2 for filter stage 3 18h eq filter gain for filter stage 4 0ch 19h eq filter coefficient a2 for filter stage 4 1ah not used 0dh 1bh eq filter coefficient a3 for filter stage 4 1ch eq filter coefficient b3 and rectify bit for filter stage 4 0eh 1dh eq filter coefficient b2 for filter stage 4 1eh eq filter gain for filter stage 5 0fh 1fh eq filter coefficient a2 for filter stage 5 20h not used 10h 21h eq filter coefficient a3 for filter stage 5 22h eq filter coefficient b3 and rectify bit for filter stage 5 11h 23h eq filter coefficient b2 for filter stage 5 24h eq filter gain for filter stage 6 12h 25h eq filter coefficient a2 for filter stage 6 26h not used 13h 27h eq filter coefficient a3 for filter stage 6 28h eq filter coefficient b3 and rectify bit for filter stage 6 14h 29h eq filter coefficient b2 for filter stage 6 2ah eq filter gain for filter stage 7 15h 2bh eq filter coefficient a2 for filter stage 7 2ch not used 16h 2dh eq filter coefficient a3 for filter stage 7 table 3. c-ram and flash memory map (continued)
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ______________________________________________________________________________________ 27 c-ram address flash address msb for c-ram lsb for c-ram 2eh eq filter coefficient b3 and rectify bit for filter stage 7 17h 2fh eq filter coefficient b2 for filter stage 7 30h not used 18h 31h* adc gain trim for gain = 1 32h not used 19h 33h* adc gain trim for gain = 2 34h not used 1ah 35h* adc gain trim for gain = 4 36h not used 1bh 37h* eq gain trim for gain = 2 38h not used 1ch 39h* eq gain trim for gain = 4 3ah* lp filter gain for filter stage 1, gain = 1, 2, or 4 1dh 3bh* lp filter coefficient a2 for filter stage 1, gain = 1, 2, or 4 3ch not used 1eh 3dh* lp filter coefficient a3 for filter stage 1, gain = 1, 2, or 4 3eh* lp filter coefficient b3 and rectify bit for filter stage 1, gain = 1, 2, or 4 1fh 3fh* lp filter coefficient b2 for filter stage 1, gain = 1, 2, or 4 40h not used 20h 41h* adc gain trim for gain = 16 42h not used 21h 43h user trim for adc gain, default = 2000h 44h not used 22h 45h not used 46h* lp filter gain for filter stage 1, gain = 16 23h 47h* lp filter coefficient a2 for filter stage 1, gain = 16 48h not used 24h 49h* lp filter coefficient a3 for filter stage 1, gain = 16 4ah* lp filter coefficient b3 and rectify bit for filter stage 1, gain = 16 25h 4bh* lp filter coefficient b2 for filter stage 1, gain = 16 4ch lp filter gain for filter stage 2 26h 4dh lp filter coefficient a2 for filter stage 2 table 3. c-ram and flash memory map (continued)
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 28 ______________________________________________________________________________________ c-ram address flash address msb for c-ram lsb for c-ram 4eh not used 27h 4fh lp filter coefficient a3 for filter stage 2 50h lp filter coefficient b3 and rectify bit for filter stage 2 28h 51h lp filter coefficient b2 for filter stage 2 52h lp filter gain for filter stage 3 29h 53h lp filter coefficient a2 for filter stage 3 54h not used 2ah 55h lp filter coefficient a3 for filter stage 3 56h lp filter coefficient b3 and rectify bit for filter stage 3 2bh 57h lp filter coefficient b2 for filter stage 3 58h lp filter gain for filter stage 4 2ch 59h lp filter coefficient a2 for filter stage 4 5ah not used 2dh 5bh lp filter coefficient a3 for filter stage 4 5ch lp filter coefficient b3 and rectify bit for filter stage 4 2eh 5dh lp filter coefficient b2 for filter stage 4 5eh lp filter gain for filter stage 5 2fh 5fh lp filter coefficient a2 for filter stage 5 60h not used 30h 61h lp filter coefficient a3 for filter stage 5 62h lp filter coefficient b3 and rectify bit for filter stage 5 31h 63h lp filter coefficient b2 for filter stage 5 64h lp filter gain for filter stage 6 32h 65h lp filter coefficient a2 for filter stage 6 66h not used 33h 67h lp filter coefficient a3 for filter stage 6 68h lp filter coefficient b3 and rectify bit for filter stage 6 34h 69h lp filter coefficient b2 for filter stage 6 6ah lp filter gain for filter stage 7 35h 6bh lp filter coefficient a2 for filter stage 7 6ch not used 36h 6dh lp filter coefficient a3 for filter stage 7 6eh lp filter coefficient b3 and rectify bit for filter stage 7 37h 6fh lp filter coefficient b2 for filter stage 7 70h not used 38h 71h not used 72h not used 39h 73h not used 74h not used 3ah 75h* adc gain trim for gain = 8 table 3. c-ram and flash memory map (continued)
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ______________________________________________________________________________________ 29 flash erase and programming when erasing or programming the flash, maintain the system clock between 14mhz and 27mhz to satisfy flash timing requirements and ensure convrun = 0. the system clock used for all digital timing is twice the adc sample clock (2 x ex clock/divider). always erase the flash page before writing new data. the procedure for flash mass erase is as follows: 1) read the flash mode register (18h); proceed when the lsb is zero. 2) write 0000h to the flash address register (19h). 3) write 60h to the flash mode register (18h). 4) wait 200ms for erase to complete. 5) ffffh = flash erased state. the procedure for flash single page erase is as follows: 1) read the flash mode register (18h); proceed when the lsb is zero. 2) write page address, set word address to 00h in the flash address register (19h). 3) write 40h to the flash mode register (18h). 4) wait 20ms for page erase to complete. 5) ffffh = flash erased state. the procedure for flash single word write is as follows: 1) read the flash mode register (18h); proceed when the lsb is zero. 2) write page and word address to the flash address register (19h). 3) write the data to the flash data in register (1ah). 4) write 20h to the flash mode register (18h). 5) read the flash mode register (18h); proceed when the lsb is zero (approx. 40?). the procedure for flash single word read is as follows: 1) read the flash mode register (18h); proceed when the lsb is zero. 2) write page and word address to the flash address register (19h). 3) write 80h to the flash mode register (18h). 4) read the flash mode register (18h); proceed when the lsb is zero (approx. 1?). 5) read the data from the flash data out register (1bh). the procedure for flash to c-ram transfer is as follows: 1) read the flash mode register (18h); proceed when the lsb is zero. 2) write a0h to the flash mode register (18h). 3) read the flash mode register (18h); proceed when the lsb is zero (approx. 1ms). 4) the content of flash is transferred to c-ram. c-ram address flash address msb for c-ram lsb for c-ram 76h not used 3bh 77h* adc gain trim for gain = 32 78h not used 3ch 79h* adc gain trim for gain = 64 7ah* lp filter gain for filter stage 1, gain = 8 3dh 7bh* lp filter coefficient a2 for filter stage 1, gain = 8 7ch not used 3eh 7dh* lp filter coefficient a3 for filter stage 1, gain = 8 7eh* lp filter coefficient b3 and rectify bit for filter stage 1, gain = 8 3fh 7fh* lp filter coefficient b2 for filter stage 1, gain = 8 table 3. c-ram and flash memory map (continued) * recommended copy to c-ram or flash for optimum custom-filter performance.
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac 30 ______________________________________________________________________________________ coefficient flash address function 51h gain for filter a, stage 3 52h a2 coefficient for filter a, stage 3 53h not used; set to 0 54h a3 coefficient for filter a, stage 3 55h b3 coefficient and rectify flag (rect) for filter a, stage 3 56h b2 coefficient for filter a, stage 3 table 4. typical filter coefficients register map (filter a, stage 3) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 xgain2gain1gain0xxxx format for filter stage gain (51h) x<15>: don?-care bit. not used. gain2:gain0<14:12>: filter gain. 000 = 2 4 = 16. 001 = 2 2 = 4. 010 = 2 0 = 1. 011 = 2 -2 = 0.25. 100 = 2 -4 = 0.0625. 101 = 2 -6 = 0.015625. 110 = 2 -8 = 0.00390625. 111 = 2 -10 = 0.0009765625. x<11:0>: don?-care bits. not used. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxxxxx digital filter coefficients
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac ______________________________________________________________________________________ 31 a2, a3, and b2 filter coefficient format (52h, 54h, 56h) filter coefficients a2, a3, and b2 are stored as 16-bit two? complement values in the -4 to (4 - 2 -13 ) range. the transfer function equation is as follows: a2 = int (n x 2 13 ) where n is the decimal coefficient value. the following are two examples of the transfer function equation: example 1: n = 2.381 a2 = int (2.381 x 2 13 ) a2 = int (19505.152) a2 = 19505 = 4c31h (two? complement) example 2: n = -2.381 a2 = int (-2.381 x 2 13 ) a2 = int (-19505.152) a2 = -19505 = b3cfh (two? complement) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 b31 b30 x rect xxxx b3 coefficient (55h) b31:b30<15:14>: filter coefficient b3. 11 = -1. 00 = 0. 01 = 1. 10 = 0. x<13>: don?-care bit. not used. rect<12>: rectify bit. 0 = bipolar output. 1 = output rectified. all samples positive. x<11:0>: don?-care bits. not used. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxxxxx power supplies, layout, and bypassing considerations for best performance, use pcbs with ground planes. ensure that digital and analog signal lines are separat- ed from each other. do not run analog and digital lines parallel to one another (especially clock lines), and do not run digital lines underneath the MAX11043 pack- age. use a single-point analog ground (star ground point) at agnd, separate from the logic ground. connect all other analog grounds and dgnd to this star ground point. do not connect other digital system grounds to this single-point analog ground. the ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. bypass all supplies to ground with high quality capacitors as close as possible to the device. chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 40 tqfn t4066-5 21-0141
MAX11043 4-channel, 16-bit, simultaneous-sampling adcs with pga, filter, and 8-/12-bit dual-stage dac maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. echo- echo+ dvdd dsp ainap aincn aincp refb ainbn ainbp refa ainan aindn aindp refc refd oscin refdach refdacl refdac refbp dvreg aout dacstep up/dwn dout sclk shdn eoc convrun din to digital supply to analog supply avdd dgnd agnd cs *see note *note: connect to agnd for single-ended operation. MAX11043 echo- echo+ *see note radar front end echo- echo+ *see note echo- echo+ *see note ext ref typical operating circuit

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